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| PRELIMINARY 3.3V ABT16-Bit Transparent D-Type Latches 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 24 25 1 48 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 54LVTH16373 Logic Diagram (PositiveLogic) 1/24 1OE/2OE 1LE/2LE 48/25 C1 1D1/2D1 47/36 1D 54LVTH16373 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2LE 2/13 1Q1/2Q1 To Seven Other Channels Logic Diagram Memory FEATURES: * 3.3V low voltage advanced BiCMOS technology (LVT) 16bit transparent D-type latches with 3-state outputs * Total dose hardness: - > 100 krad (Si), dependent upon space mission * Single event effect: - SELTH : No LU > 119 MeV/mg/cm2 * Package: 48 pin RAD-PAK(R) flat package * Operating temperature range: - 55 to 125C * Distributed VCC and GND pin configuration minimizes highspeed switching noise * Supports mixed-mode signal operation - 5V input and output voltages with 3.3V VCC * Supports unregulated battery operation down to 2.7V * Typical VOLP (output ground bounce) < 0.8V at VCC=3.3V, TA=25C * Latch-up performance exceeds 500mA per JEDEC standard * Supports live insertion * Bus-hold data inputs eliminate the need for external pullup resistors DESCRIPTION: Maxwell Technologies' 54LVTH16373 16-bit transparent Dtype latches with 3-state output features a greater than 100 krad (Si) total dose tolerance, dependent upon space mission. The 54LVTH16373 is designed for low voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The 54LVTH16373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is low, the Q output are latched at the levels set up at the data (D) inputs. When LE is high, the Q outputs follow the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches TABLE 1. PINOUT DESCRIPTION PIN 1, 24 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 25, 48 26, 27, 29, 30, 32, 31, 32, 33, 35, 36 37, 38, 40, 41, 43, 44, 46, 47 SYMBOL 1OE-2OE 1Q1-1Q8 GND VCC 2Q1-2Q8 2LE-1LE 2D8-2D1 1D8-1D1 Output Enable Outputs Ground Power Supply Outputs Latch Enable Inputs Inputs DESCRIPTION 54LVTH16373 Memory TABLE 2. 54LVTH16373 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage range Input voltage range 1 Voltage range applied to any output in the high state or power-off state 1 Current into any output in the low state Current into any output in the high state 2 Input clamp current (VI < 0) Output clamp current (VO < O) Maximum power dissipation at TA = 55C 3 Storage temperature range SYMBOL VCC VI VO IO IO IIK IOK PD TS MIN -0.5 -0.5 -0.5 ------65 MAX 4.6 7 7 96 48 -50 -50 0.85 150 UNIT V V V mA mA mA mA mW C 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 2 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches TABLE 3. DELTA LIMITS PARAMETER ICC(OL) ICC(OH) ICC(OD) VARIATION 10% of specified value in Table 5 10% of specified value in Table 5 10% of specified value in Table 5 54LVTH16373 TABLE 4. 54LVTH16373 RECOMMENDED OPERATING CONDITIONS 1 PARAMETER Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate (outputs enabled) Operating free-air temperature SYMBOL VCC VIH VIL VI IOH IOL TA MIN 2.7 2 ------55 MAX 3.6 -0.8 5.5 -24 68 10 125 UNIT V V V V mA mA ns/V C Memory t/v 1. Unused control inputs must be held high or low to prevent them from floating. TABLE 5. 54LVTH16373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA = -55 to 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Input Clamp Voltage High-Level Output Voltage SYMBOL VIK VOH VCC = 2.7 VCC = 2.7V to 3.6V VCC = 2.7V VCC = 3V, Low-Level Output Voltage VOL VCC = 2.7V VCC = 3V Input Current II VCC = 0 or 3.6V VCC = 3.6V VCC = 3.6V TEST CONDITIONS II = -18mA IOH = -100A IOH = -8mA IOH = -32mA IOL = 100A IOL = 24mA IOL = 16mA IOL = 32mA VI = 5.5V VI = VCC or GND VI = VCC VI = 0 1000603 12.19.01 Rev 1 MIN -VCC -0.2 2.4 2.0 ----Control Inputs Data Inputs ---- MAX -1.2 ---0.2 0.5 0.4 0.5 10 1 1 -5 UNIT V V V A All data sheets are subject to change without notice 3 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches 54LVTH16373 MIN MAX --5 -5 100 100 0.19 5 0.19 0.2 10 15 mA pF pF A A A A mA UNIT A TABLE 5. 54LVTH16373 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA = -55 to 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Hold Current Output Disabled Leakage Current - High Output Disabled Leakage Current - Low Power Up Current Power Down Current Supply Current SYMBOL II(HOLD) VCC = 3V IOZH IOZL IOZPU2 IOZPD2 ICC VCC = 3.6V, VO = 3V VCC = 3.6V, VO = 0.5V VCC = 0 to 1.5V, VO = 0.5V to 3V, OE = don't care VCC = 1.5V to 0, VO = 0.5V to 3V, OE = don't care VCC = 3.6V IO = 0 VI = VCC or GND Outputs high Outputs low Outputs disabled Delta Supply Current Input Capacitance Input Output Capacitance TEST CONDITIONS VI = 0.8V VI = 2V Data Inputs 75 -75 ----------- Memory ICC 1 VCC = 3V to 3.6V, One input at VCC -0.6V, Other inputs at VCC or GND C I2 CO2 VI = 3V or 0 VO = 3V or 0 1. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 2. Guaranteed by design. TABLE 6. 54LVTH16373 AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA = -55 to 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Pulse duration, LE high Setup time, data before LEO Hold time, data after LEO Propagation Delay Time D to Q Propagation Delay Time LE to Q Output Enable Time OE to Q SYMBOL tW tSU tH tPLH tPHL tPLH tPHL tPZH tPZL VCC = 3.3V 0.3V MIN 3.3 0.5 1.8 2.7 2.9 3.6 4.7 2.9 3 MAX ---5 4.9 6 6.9 5.3 5.1 MIN 3.3 0.5 2 ------VCC = 2.7V MAX ---5.7 5.7 6.8 8.8 6.3 5.9 ns ns ns ns ns ns UNIT 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 4 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches 54LVTH16373 VCC = 2.7V UNIT 7.6 5.9 ns TABLE 6. 54LVTH16373 AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 10%, TA = -55 to 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Output Disable Time OE to Q SYMBOL tPHZ tPLZ VCC = 3.3V 0.3V MIN 4.3 4 MAX 6.8 5.8 MIN --- MAX TABLE 7. FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z Memory FIGURE 1. LOAD CIRCUIT FOR OUTPUTS Figure Note: 1. CL includes probe and jig capacitance. PARAMETER MEASUREMENT INFORMATION TEST TPLH/TPHL TPLZ/TPZL TPHZ/TPZH S1 Open 6V GND 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 5 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches FIGURE 2. PULSE DURATION 54LVTH16373 FIGURE 3. SETUP AND HOLD TIMES Memory FIGURE 4. PROPAGATION DELAY TIMES INVERTING AND NON-INVERTING OUTPUTS 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 6 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches 54LVTH16373 FIGURE 5. ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING FIGURE NOTES: 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 5, tr < 2.5 ns, tf < 2.5 ns. 4. The outputs are measured one at a time with one transition per measurement. Memory 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 7 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches 54LVTH16373 Memory 48 PIN RAD-PAK(R) FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.275 0.013 0.005 0.144 0.008 0.004 -0.370 -0.200 0.075 DIMENSION NOM 0.160 0.010 0.006 0.620 0.380 -0.210 0.085 0.025 BSC 0.285 0.019 0.018 48 0.295 0.045 -MAX 0.176 0.014 0.007 0.640 0.390 0.410 0.220 -- F48-01 Note: All dimensions in inches 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 8 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches Important Notice: 54LVTH16373 These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts. Memory 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 9 (c)2001 Maxwell Technologies All rights reserved. PRELIMINARY 3.3V ABT 16-Bit Transparent D-Type Latches Product Ordering Options Model Number 54LVTH16373 RP F X Feature 54LVTH16373 Option Details Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25C) I = Industrial (testing @ -55C, +25C, +125C) Memory Package F = Flat Pack Radiation Feature RP = RAD-PAK(R) package Base Product Nomenclature 3.3V ABT 16-Bit Transparent D-Type Latches 1000603 12.19.01 Rev 1 All data sheets are subject to change without notice 10 (c)2001 Maxwell Technologies All rights reserved. |
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